FPGA design of second release of Gigabit Ethernet router

Client:

• Nokia Siemens Networks GmbH & Co. KG

Task:

• As in the first release of the Gigabit Ethernet router the core functionality of the OLT was to be implemented into an FPGA. The most challenging part was to integrate six up- and downstream channels with 2.5 GBit/s each. This results in an overall bandwidth of 30 GBit/s on a single FPGA. Main parts of each channel were a complex Ethernet MAC/VLAN address translation and an IP anti-spoofing unit.

Platform:

• XILINX Virtex-5 LX85T™ FPGA