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CHIP-ON-MEMS- HETEROGENEOUS INTEGRATION OF MEMS AND CIRCUITS


http://www.intl-sensor.com    Times:2008/6/19 13:41:11    Count : 1772 Times

New verified integration concept

VTI has verified a new heterogeneous integration concept for combining MEMS devices and integrated circuits: chip-on-MEMS or CoM. The concept is based on a combination of VTI's wafer level encapsulated 3D MEMS, wafer level packaging (WLP) technology and chip-on wafer technology. All these elements of CoM have existed for a few years. Combining them in an innovative way solves the tough packaging problem: how to combine cost efficiently MEMS with circuits.

The technology consists of steps of applying a redistribution and isolation layers on the MEMS wafer, dropping 300 micron solder balls, flip-chipping thinned ASICs and finally passivating the gap between the ASIC and MEMS by underfilling. The MEMS-wafer was probed so that only known good sites will be populated. After completion of the process the wafer will be diced and the final test performed when the dies are still on the dicing tape. Sensors will be also calibrated while still on the tape..

The first fully functional MEMS device based on CoM has a foot print of less than 4 mm2 and height 1 mm. The technology is now ready for product design and industrialization.


A new direction for system integration

The flip-chipped CoM is the first step on VTI's heterogeneous integration roadmap. It is a radical step away from the conventional packaging, which relies on integration on a carrier, either a pre-molded housing, a lead frame or a substrate. Eventually CoM will result in smaller size and lower cost than any carrier based packaging. All packaging will be just an extension of the processes of a wafer-fab.

CoM is not the first ever demonstration of wafer level combination of MEMS and circuits. But it solves many issues that are present with the earlier approaches. In CoM the MEMS-device and the ASIC are fully isolated in manufacturing: both can be 100% tested prior to combining. No area is wasted due to size mismatch. No area is wasted for the sealing between MEMS and the circuit.

The first implementation of CoM requires that the MEMS die is somewhat larger than the circuit and the I/O-count will be limited. After the flip-chipped CoM VTI will implement embedded CoM. Very thin dies will be embedded in polymer layers on the MEMS wafer. Interconnections between layers will be made by deposited metal films. Several circuits can be stacked. A real microsystem with MEMS and several circuits is possible. This is the technology for smart MEMS.

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